Person: Zencir, Ertan
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Dr. Öğr. Üyesi
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Zencir
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Ertan
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Ertan ZENCİR
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Publication Ultra-Wide Bandwidth Fully Differential CMOS Opamp with a Novel Bandwidth Extension Technique for SoC Active Filter Applications(WORLD SCIENTIFIC PUBL CO PTE LTD, 2021) Kayanselcuk, Toprak; Zencir, Ertan; Zencir, Ertan; Turk Hava Kurumu University; Turkish Aeronautical AssociationAn ultra-wide bandwidth fully differential two-stage 65nm CMOS operational amplifier (Opamp) is presented, which uses a novel bandwidth extension technique called pole duplication. This technique is based on relocating the dominant pole with the same location with a non-dominant pole and adjusting 3-dB frequency and stability with a compensation network. Simulation results show that the proposed Opamp has 103MHz 3-dB bandwidth with a 2pF load capacitor. It consumes 9mA current from 1.2-V supply. Transition frequency of 2.4GHz and a gain of 29dB is accomplished. A 2pF load capacitance can be driven at a phase margin of 55 degrees. The suggested pole duplication technique is used to achieve higher 3-dB cut-off frequencies by adjusting the load capacitor. Fully differential two-stage Opamp is presented, which uses a novel bandwidth extension technique, is suitable for SoC active filter applications with 40 mu mx60 mu m layout area and ultra-wide 3-dB bandwidth.Publication Error Performance of Subsampling Digital Power Estimation for Integrated Receivers(WORLD SCIENTIFIC PUBL CO PTE LTD, 2022) Khaleel, Aymen; Zencir, Ertan; Aksoy, Hasan; Zencir, Ertan; Aksoy, Hasan; Koc University; Turk Hava Kurumu University; Turkish Aeronautical AssociationEstimation of signal power levels at the output of integrated receiver building blocks is a vital function as the block voltage or power gains are set based on sensed power levels to maintain constant levels at block outputs in the receiver chain. RF and IF level real-time gain settings are determined with Automatic Gain Control (AGC) loops. AGC loop circuit topologies are usually based on analog detection circuits. These analog power detection circuits are based on techniques such as envelope detection, and logarithmic amplification usually accompanied by severe accuracy issues such as Process, Voltage and Temperature (PVT) spreads preventing correct gain adjustments. Adopting a dominantly digital approach to detect the signal power would ensure a significant reduction in PVT spreads. This work presents a review of the subsampling digital power estimation to create low power digital power estimations alternative to analog methods. The simulations of the method are applied to an AM and a 64-QAM signal. Simulation results show that the power estimation error is within the acceptable level of +/- 1 dB.Publication A Low Spur 5.9-GHz CMOS Frequency Synthesizer with Loop Sampling Filter for C-V2X Applications(WORLD SCIENTIFIC PUBL CO PTE LTD, 2023) Ulusoy, Emre; Zencir, Ertan; Zencir, Ertan; Turkiye Bilimsel ve Teknolojik Arastirma Kurumu (TUBITAK); Istanbul Technical University; Turkish Aeronautical Association; Turk Hava Kurumu UniversityIn this paper, a very low spur 5.9-GHz integer-N frequency synthesizer designed for a Cellular Vehicle-to-Everything (C-V2X) receiver is presented. The PLL is referenced to a 10-MHz crystal oscillator and the design is implemented in a 65-nm CMOS process. The output of the synthesizer has differential quadrature topology and provides the local oscillator signal to a downconverter mixer of C-V2X receiver. Post-layout simulations show that the reference spurs are better than -88dBc through loop sampling technique which was implemented in a 11.8-GHz VCO design for the first time to the best of our knowledge. The best spur level without the loop sampling technique applied is limited to -55dBc. Using the loop sampling technique provides a spur reduction of 33dB which is a significant improvement at this frequency. Based on post-layout simulations, the design has a phase noise of -97/-99/-114dBc for 10kHz/100kHz/1MHz frequency offsets, respectively, which presents competitive numbers with the designs in the literature. The design has 1.2-V nominal supply voltage for the analog and digital blocks. The total power dissipation of the synthesizer core is 6mW from a 1.2-V supply while the output buffers driving a 100-fF load consumes 18mW.Publication An embedded 65 nm CMOS baseband IQ 48 MHz-1 GHz dual tuner for DOCSIS 3.0(Institute of Electrical and Electronics Engineers (IEEE), 2010-04) Francesco Gatta; Ray Gomez; Young Shin; Takayuki Hayashi; Hanli Zou; James Chang; Leonard Dauphinee; Jianhong Xiao; Dave Chang; Tai-hong Chih; Massimo Brandolini; Dongsoo Koh; Bryan Hung; Tao Wu; Mattia Introini; Giuseppe Cusmai; Ertan Zencir; Frank Singor; Hans Eberhart; Loke Tan; Bruce Currivan; Lin He; Peter Cangiane; Pieter Vorenkamp; Zencir, ErtanPublication UHF RF Front-End Circuits in 0.35-μm Silicon on Insulator (SOI) CMOS(Springer Science and Business Media LLC, 2005-12) Ertan Zencir; Te-Hsin Huang; Ahmet Tekin; Numan S. Dogan; Ercument Arvas; Zencir, ErtanPublication New anti-collision protocol for RFID-based student attendance system(IEEE, 2018) Sharabaty, Hassan; Zencir, Ertan; Hameed, Ghassan Ali; Zencir, Ertan; Turk Hava Kurumu University; Turkish Aeronautical AssociationThe importance of Radio Frequency Identification (RFID) systems comes from its ability to communicate remotely with others devices in spite of barriers, obstacles, walls or even the water. RFID also offers a highspeed processing for all operations performed by these systems. The main parts of any RFID system are tags and reader. However, the tags collision problem affects the performance and the accuracy of the identification process. In this paper, we propose a new anti-collision protocol to reduce the tags collisions that take place in RFID based student attendance system. Firstly, development of the two conventional anti-collusion methods is proposed: Dynamic Framed Slotted ALOHA (DFSA), and Basic Framed Slotted ALOHA (BFSA), then, we combine both methods in a novel anti-collision protocol to accelerate the identification process. Comparing to other conventional anti-collusion techniques in the literature, the simulation results show that our proposed protocol decreased the time and slots consumption of the authentication process by 26%. The throughput of the identification process is also increased by approximately 10%, while the number of collided tags are reduced by 49%.Publication A low-power 65-nm CMOS mixer linearized with IM2 injection for V2X applications(SPRINGER, 2022) Ozkan, Bahadir; Zencir, Ertan; Zencir, Ertan; Turkiye Bilimsel ve Teknolojik Arastirma Kurumu (TUBITAK); Turkish Aeronautical Association; Turk Hava Kurumu UniversityIn this paper, high linearity, low power down-conversion mixer is presented with a 65-nm CMOS process for vehicle-to-everything (V2X) applications. 5G NR V2X standard has a carrier frequency of 5.9 GHz with 10 and 20 MHz narrow bandwidth options. The mixer design uses a double-balanced topology with a second-order intermodulation injection linearization technique to improve the linearity performance. The charge injection method is also used to decrease the noise figure of the circuit. The designed circuit shows a single sideband integrated noise figure of 16.5 dB with a total conversion gain of 2 dB. The third-order input intercept point is obtained as 19.86 dBm. The design consumes a total current of 6 mA from a 1.2-V supply voltage. To the best of the authors' knowledge, this technique is the first applied to mixer design that has been designed for 5G NR based C-V2X applications in the literature.Publication Self calibrated cooler-less microbolometer readout architecture(ELSEVIER, 2022) Gulden, Mehmet Ali; Zencir, Ertan; Cavus, Enver; Zencir, Ertan; Aselsan; Ankara Yildirim Beyazit University; Turkish Aeronautical Association; Turk Hava Kurumu UniversityThis study describes a new method to compensate bias heating effects for microbolometer readout circuits using a finely adjustable CMOS resistance as a reference. The proposed self calibrated cooler-less structure dynamically modifies CMOS resistance during integration time. This compensation structure also includes a feedback loop, which forces the oscillators to work in the linear region. The proposed self calibration circuit is designed and simulated using a 65-nm process node, and achieves 40 mK NETD (Noise Equivalent Temperature Difference) value for one percent resistance non-uniformity of pixel resistance values across one row. The layout area of this circuit occupies approximately one third of the layout area used by classical readout circuits. The circuit dissipates one third of power compared with classical microbolometer readout approaches.Publication A High-Speed Fully Differential Telescopic Op-Amp for Active Filter Designs in V2X Applications(WORLD SCIENTIFIC PUBL CO PTE LTD, 2022) Barin, Furkan; Zencir, Ertan; Zencir, Ertan; Turkiye Bilimsel ve Teknolojik Arastirma Kurumu (TUBITAK); Turkish Aeronautical Association; Turk Hava Kurumu UniversityIn this paper, an ultra-wideband fully differential two-stage telescopic 65-nm CMOS op-amp is presented, which uses low-voltage design techniques such as level shifter circuits and low-voltage cascade current mirrors. The designed op-amp consists of two stages. While the telescopic first stage provides high speed and low swing, the second stage provides high gain and large swing. Common-mode feedback circuits (CMFB), which contain five transistors OTA and sensing resistors, are used to set the first-stage output to a known value. The designed two-stage telescopic operational amplifier has 41.04 dB lower frequency gain, 1.81 GHz gain-bandwidth product (GBW) and 51.9 degrees phase margin under 5 pF load capacitance. The design consumes a total current of 11.9 mA from a 1.2-V supply voltage. Presented fully differential two-stage telescopic op-amp by using low-voltage design techniques is suitable for active filter in vehicle-to-everything (V2X) applications with 120 mu m x 55 mu m layout area.Publication Opportunities and challenges inRCSmeasurement of 9-mm bullet model with77 GHzmmwaveCOTSradar systems(WILEY, 2020) Ahmed, Badar-ud-din; Kara, Ali; Zencir, Ertan; Benzaghta, Mohamed; Zencir, Ertan; Atilim University; Turkish Aeronautical Association; Turk Hava Kurumu UniversityThis article indicates a thus far unexplored area of applied research and development to the application and system engineers and researchers from broad engineering backgrounds. Results of a study are presented for measurement of calibrated Radar Cross Section (RCS) of a 9-mm bullet (projectile) model by using a commercial-of-the-shelf (COTS) millimeter wave Frequency Modulated Continuous Wave (FMCW) radar system operating in 77 to 81 GHz frequency range. The calibrated RCS variation against the aspect angle is measured experimentally, analyzed, and compared with the simulation results which shows fair matching between the two. The opportunities and challenges attached with the use of such COTS systems for development of Hostile Fire Indication (HFI) systems are discussed. This bullet type and this mmwave frequency has not been thus far studied and reported in literature. This may motivate interested individuals/entities to try to measure (at acceptable accuracy before anechoic chamber measurements) RCS of similar low-size objects by using such low-cost COTS platforms.